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3C277 mc141800a motorola product preview lcd segment / common driver cmos mc141800a is a cmos lcd driver which consists of 193 high voltage lcd driving signals to drive 128 segment and 65 common display. it has 6800-series parallel, iic serial interface and serial peripheral interface (spi) capability for operating with general mcu. besides the general lcd driver features, it has on chip lcd smart bias divider circuit such that minimize external component required in applications. mc141800at: tab (tape automated bonding) MCC141800AZ: gold bump die ? single supply operation, 2.4 v - 3.5 v ? maximum 16.5v lcd driving output voltage ? low current stand-by mode (<1ua) ? on chip internal dc/dc converter / external power supply ? smart bias divider ? 4x / 5x dc-dc converter ? 8 bit 6800-series parallel interface, 1 mhz iic serial interface and serial peripheral interface (spi) ? on chip oscillator ? graphic mode operation ? on chip 128 x 65 display data ram ? master clear ram ? low power icon mode (128 icons, <25ua) ? display masks for implementation of blinking effect ? 1 to 65 selectable multiplex ratio ? 1:7 / 1:9 bias ratio ? re-mapping of row and column drivers ? 16 level internal contrast control ? external contrast control ? built-in temperature compensation circuit ? selectable display waveform: type b or type c waveform ? 2v icon mode display on mc141800a ordering information mc141800at 70 mm tab MCC141800AZ gold bump die this document contains information on a product under development. motorola reserves the right to change or discontinue this product without notice. tab mc141800at MCC141800AZ gold bump die motorola semiconductor technical data rev o 2/97
motorola 3C278 mc141800a lcd driving voltage generator 4x and 5x dc/dc converter, voltage regulator, smart bias divider, contrast control, temperature compensation com0 to com64 seg0~seg127 osc1 osc2 dvss dvdd res r/ w d0~d7 vll6 vll2 vcc vr vf c1p c3p c1n c3n avdd avss gddram 65 x 128bits command decoder parallel / serial interface command interface display timing generator 128 bit latch 65 bit latch hv buffer cell level shifter level selector clk d/ c ce s/ p block diagram
3C279 mc141800a motorola mc141800at pin assignment (copper view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 dvdd s/ p res d/ c r/ w d7/iic/ spi d6 d5 d4/dout d3/din d2/a2 d1/a1 d0/sda clk ce vf vr c1p c1n c2p c2n c3p c3n nc nc vll2 vll3 nc nc nc nc vll4 vll5 vll6 osc1 dvss nc nc vcc avss osc2 avdd com31 com30 com29 com28 com27 com2 com1 com0 com64b seg127 seg126 seg125 seg124 seg123 seg66 seg65 seg64 seg63 seg62 seg61 seg2 seg1 seg0 com32 com33 com34 com61 com62 com63 com64a dummy dummy dummy dummy 236 235 234 233 232 207 206 205 204 203 202 201 200 199 142 141 140 139 138 137 78 77 76 75 74 73 46 45 44 43 mirror design tab die encapsulant copper polyimide
motorola 3C280 mc141800a input pad, 65 x 65 (um) output pad, 42 x 100 (um) die pad layout for mc141800a com55 com56 . . com63 com64a avdd osc2 avss vcc vcc dvss dvss osc1 dvss vll6 vll6 vll5 vll5 vll4 vll4 vll3 vll3 vll2 vll2 c3n c3p c2n c2p c1n c1p vr vf avss avss avdd avdd com31 . . . . . com22 com32 com33 . . . . . . . . . . . com53 com54 seg0 seg1 seg2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . seg126 seg127 com64b com0 . . . . . . . . . . . com20 com21 gold bump size : mc141800a dvss dvss dvss dvss dvss dvss d/c res s/p dvdd dvss dvss dvdd dvdd ce clk clk d0 d0 d1 d2 d3 d4 d5 d6 d7 r/w dvss dvss dvss dvss dvss dvss dvss dvss dvss dvss dvss dvss dvss dvss dvss dvss dvss dvss dvss m
3C281 mc141800a motorola maximum ratings* (voltages referenced to v ss , t a =25?c) symbol parameter value unit av dd ,dv dd supply voltage -0.3 to +4.0 v v cc v ss -0.3 to v ss +16.5 v v in input voltage v ss -0.3 to v dd +0.3 v i current drain per pin excluding v dd and v ss 25 ma t a operating temperature -30 to +85 ?c t stg storage temperature range -65 to +150 ?c * maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the limits in the electrical characteristics tables or pin descrip- tion section. v ss = av ss = dv ss (dv ss = v ss of digital circuit, av ss = v ss of analogue circuit) v dd = av dd = dv dd (dv dd = v dd of digital circuit, av dd = v dd of analogue circuit) this device contains circuitry to protect the inputs against damage due to high static voltages or elec- tric ?elds; however, it is advised that normal precau- tions to be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. for proper operation it is recom- mended that v in and v out be constrained to the range v ss < or = (v in or v out ) < or = v dd . reliability of operation is enhanced if unused input are con- nected to an appropriate logic voltage level (e.g., either v ss or v dd ). unused outputs must be left open. this device may be light sensitive. caution should be taken to avoid exposure of this device to any light source during normal operation. this device is not radiation protected. electrical characteristics (voltage referenced to v ss , v dd =2.4 to 3.5v, t a =25?c) symbol parameter test condition min typ max unit dv dd av dd logic circuit supply voltage range voltage generator circuit supply voltage range (absolute value referenced to v ss ) 2.4 2.4 3.0 - 3.5 3.5 v v i ac i dp i sb i icon access mode supply current drain (av dd + dv dd pins) display mode supply current drain (av dd + dv dd pins) standby mode supply current drain (av dd + dv dd pins) icon mode supply current drain (av dd + dv dd pins) v dd =3.0v, internal dc/dc converter on, 5x dc/dc converter enabled, r/ w accessing, t cyc =1mhz, osc. freq.=50khz, display on. v dd =3.0v, internal dc/dc converter on, 5x con- verter enabled, r/w halt, osc. freq.=50khz, dis- play on. v dd =3.0v, display off, oscillator disabled, r/ w halt. v dd =3.0v, internal oscillator, oscillator enabled, display on, icon on, r/ w halt, freq.=50khz. - - - - 500 300 tbd tbd tbd tbd 1 25 m a m a m a m a v cc v lcd lcd driving internal dc/dc converter output (v cc pin) lcd driving voltage input (v cc pin) display on, dc/dc converter enabled, osc. freq.= 50khz, internal regulator enabled, divider enabled. internal dc/dc converter disabled. 7 7 15 15 16.5 16.5 v v v icon low power icon mode voltage -2-v v oh1 v ol1 v r1 v r2 output high voltage (d0-d7, osc2) output low voltage (d0-d7, osc2) lcd driving voltage source (v r pin) lcd driving voltage source (v r pin) i out =100 m a i out =100 m a internal regulator enabled (v r voltage depends on int/ext contrast control) internal regulator disable. 0.9*v dd 0 0 - - - - floating v dd 0.1*v dd v cc -0.5 - v v v v
motorola 3C282 mc141800a electrical characteristics (voltage referenced to v ss , v dd =2.4 to 3.5v, t a =25?c) * the formula for the temperature coefficient is: symbol parameter test condition min typ max unit v ih1 v il1 input high voltage ( res, osc2, clk, ce, d0-d7,r/ w, d/ c, s/ p, osc1) input low voltage ( res, osc2, clk, ce, d0-d7, r/ w, d/ c, s/ p, osc1) 0.8*v dd 0 - - v dd 0.2*v dd v v v ll6 v ll5 v ll4 v ll3 v ll2 v ll6 v ll5 v ll4 v ll3 v ll2 v ll6 v ll5 v ll4 v ll3 v ll2 lcd display voltage output (v ll6 , v ll5 , v ll4 , v ll3 , v ll2 pins) lcd display voltage output (v ll6 , v ll5 , v ll4 , v ll3 , v ll2 pins) lcd display voltage input (v ll6 , v ll5 , v ll4 , v ll3 , v ll2 pins) smart bias divider enabled, 1:9 bias ratio smart bias divider enabled, 1:7 bias ratio external voltage generator, smart bias divider dis- able - - - - - - - - - - 7 0 0 0 0 v r 8/9*v r 7/9*v r 2/9*v r 1/9*v r v r 6/7*v r 5/7*v r 2/7*v r 1/7*v r - - - - - - - - - - - - - - - v cc v ll6 v ll5 v ll4 v ll3 v v v v v v v v v v v v v v v i oh i ol i oz output high current source (d0-d7, osc2) output low current drain (d0-d7, osc2) output tri-state current drain source (d0-d7, osc2) v out =v dd -0.4v v out =0.4v 50 - -1 - - - - -50 1 m a m a m a i il /i ih input current ( res, osc2, clk, d0-d7, r/ w, d/ c, s/ p, osc1) -1 - 1 m a c in input capacitance (osc1, osc2, all logic pins) - 5 7.5 pf v cn internal contrast control (v r output voltage) internal regulator enabled, internal contrast control enabled. (16 voltage levels controlled by software. each level is typically 1.5% of the internal regulator output voltage.) - 12 - % ptc0 ptc1 ptc2 ptc3 temperature coef?cient compensation flat temperature coef?cient temperature coef?cient 1* temperature coef?cient 2* temperature coef?cient 3* (tc1=0, tc2=0, internal regulator disabled.) (tc1=0, tc2=1, internal regulator enabled.) (tc1=1, tc2=0, internal regulator enabled.) (tc1=1, tc2=1, internal regulator enabled.) - - - - 0.0 -0.18 -0.22 -0.35 - - - - % % % % tc(%)= vr at 50?c - vr at 0?c 50?c - 0?c x 1 vr at 25?c x100%
3C283 mc141800a motorola figure 1. internal oscillator frequency relationship with external resistor value ac electrical characteristics (t a =25?c, voltage referenced to v ss , av dd =dv dd =3v) symbol parameter test condition min typ max unit f osc oscillation frequency of display timing generator 60hz frame frequency either external clock input or internal oscillator enabled 45 60 55 khz f frm frame frequency graphic display mode, normal frequency mode, 65 - 49 mux graphic display mode, half frequency mode, 65 - 49 mux graphic display mode, normal frequency mode, 48 - 33 mux graphic display mode, half frequency mode, 48 - 33 mux graphic display mode, normal frequency mode, 32 - 2 mux graphic display mode, half frequency mode, 32 -2 mux 6-phase low power icon mode, normal frequency mode 6-phase low power icon mode, half frequency mode 4-phase low power icon mode, normal frequency mode 4-phase low power icon mode, half frequency mode - - - - - - - - - - - - - - - - - - - - hz hz hz hz hz hz hz hz hz hz osc internal oscillation frequency with different value of feedback resistor internal oscillator enabled, v dd within operation range see figure 1 for the relationship f osc 15 * mux f osc 960 f osc 1920 f osc 1024 f osc 2048 f osc 30 * mux f osc 23 * mux f osc 46 * mux f osc 30 * mux f osc 60 * mux 100k 500k 1.0m 1.5m 2.0m resistor value between osc1 and osc2 ( w ) oscillation frequency (hz) 260k 90k 70k 50k 30k 10k 280k
motorola 3C284 mc141800a table 3. parallel timing characteristics (t a =-30 to 85?c, dv dd =2.4 to 3.5v, v ss =0v) symbol parameter min typ max unit t cycle clock cycle time 1000 - - ns t as address setup time 90 - - ns t ah address hold time 60 - - ns t dsw write data setup time 210 - - ns t dhw write data hold time 75 - - ns t dsr read data setup time 250 - - ns t dhr read data hold time 75 - - ns t acc access time - - 250 ns pw el enable low pulse width 390 - - ns pw eh enable high pulse width 390 - - ns t r rise time - - 45 ns t f fall time - - 45 ns valid data t cycle t dsw t as t ah t dhr t acc clk d/ c d0-d7 ce valid data d0-d7 (write data to driver) (read data from driver) t dhw pw eh pw el t r t f t dsr r/ w figure 2. parallel 6800-series interface timing characteristics
3C285 mc141800a motorola table 4. iic serial timing characteristics (t a =-30 to 85?c, dv dd =2.4 to 3.5v, v ss =0v) symbol parameter 100khz 400khz 1mhz unit min typ max min typ max min typ max t cycle clock cycle time 10 - - 2.5 - - 1 - - m s t hstart start condition hold time 4.0 - - 0.6 - - 0.3 - - m s t hd data hold time 500 - - 300 - - 150 - - ns t sd data setup time 250 - - 100 - - 50 - - ns t sstart start condition setup time (only relevant for a repeated start condition) 4.7 - - 0.6 - - 0.3 - - m s t sstop stop condition setup time 4.0 - - 0.6 - - 0.3 - - m s t r rise time for data and clock pin - - 1000 - - 300 - - 150 ns t f fall time for data and clock pin - - 300 - - 300 - - 150 ns t idle idle time before a new transmission can start 4.7 - - 1.3 - - 0.6 - - m s figure 3. iic serial interface timing characteristics clk sda t cycle t hstart t hd t idle t sstop t f t r t sstart ( ) ( ) ( ) ( ) t sd
motorola 3C286 mc141800a figure 4. iic serial interface input protocol (write data to driver) figure 5. iic serial interface output protocol (read data from driver) address d/ cr/ w ack stop condition data ack ack 1 - 8 9 p ( ) ( ) ( ) ( ) ( ) ( ) 1 clk sda start condition s (from controller) sda (from driver) a1 a2 ( ) ( ) ( ) ( ) ( ) ( ) (a0) 23456789 address d/ cr/ w ack stop condition data ack ack 1 - 8 9 p ( ) ( ) ( ) ( ) ( ) ( ) 1 clk sda start condition s (from controller) sda (from driver) a1 a2 ( ) ( ) ( ) ( ) ( ) ( ) (a0) 23456789
3C287 mc141800a motorola table 5. spi timing characteristics (t a =-30 to 85?c, dv dd =2.4 to 3.5v, v ss =0v) symbol parameter min typ max unit t cycle clock cycle time 1000 - - ns t lead enable lead time 500 - - ns t lag enable lag time 500 - - ns t dsw write data setup time 100 - - ns t dhw write data hold time 100 - - ns t dvr read data valid time - - 240 ns t dhr read data hold time 10 - - ns t acc access time - - 120 ns t dis disable time - - 240 ns t clkl clock low time 380 - - ns t clkh clock high time 380 - - ns t r rise time - - 100 ns t f fall time - - 100 ns figure 6. spi timing characteristics t cyc clk dout din ce ( ) ( ) ( ) ( ) ( ) ( ) t lead t clkh t dis t lag t dhw t dsw t acc t dhr t dvr t clkl t f t r msb lsb ( ) ( ) msb lsb ( ) ( ) ( ) ( )
motorola 3C288 mc141800a s/ p (serial / parallel interface) this pin is an input pin. the pin is sampled out when reset to determine what type of interface is desired. the s/ p pin input high for serial interface while input low for parallel interface. d/ c (data / command) if parallel interface is selected, this input pin acknowledges the lcd driver the input at d0-d7 is data or command. input high for data while input low for command. if serial interface is selected, float this pin. clk (input clock) this pin is normal low clock input. if parallel interface is selected, data on d0-d7 are latched at the falling edge of clk. if iic serial interface is selected, data on sda is latched at the falling edge of clk. if spi is selected, data on din and dout are latched at the fall- ing edge of clk. res (reset) a low input pulse to this pin resets the internal status of the driver (same as power on reset). the minimum pulse width is 10 m s. ce (chip enable) if parallel interface is selected, this input pin is used for chip enable. if iic serial interface is selected, leave this pin float and it will be internally tied to vdd. d0 - d7 (data) this bi-directional bus is used for data / command transferring. if parallel interface is selected, d0 - d7 are connected directly to mcu for data transfer. when serial interface is selected, d7 (iic/ spi) is an input pin to determine which type of serial interface is desired. the iic/ spi pin high indicates iic interface is used. the iic/ spi pin low indicates spi is used. when iic serial interface is selected, d0 (sda) is connected directly to mcu for data transfer, d1 (a1) and d2 (a2) are used to define the 2 bit programmable address. the address of this device is 0111xyab where x, y, a, b represent a2, a1, d/ c and r/ w respec- tively. when spi is selected, d3 (din) is used to write data / command from mcu to driver and d4 (dout) is used to read data / command to mcu from driver. r/ w (read / write) if parallel interface is selected, this is an input pin. to read the dis- play data ram or the internal status (busy / idle), pull this pin high. the r/ w input low indicates a write operation to the display data ram or to the internal setup registers. if serial interface is selected, let this pin float. osc1 (oscillator input) for internal oscillator mode, this is an input for the internal low power rc oscillator circuit. in this mode, an external resistor of cer- tain value should be connected between the osc1 and osc2 pins for a range of internal operating frequencies (refer to figure 1). for external oscillator mode, osc1 should be left open. osc2 (oscillator output / external oscillator input) for internal oscillator mode, this is an output for the internal low power rc oscillator circuit. for external oscillator mode, osc2 will be an input pin for external clock and no external resistor is needed. vll6 - vll2 group of voltage level pins for driving the lcd panel. they can either be connected to external driving circuit for external bias supply or connected internally to built-in divider circuit if internal divider is enable. c1n and c1p, c2n and c2p, c3n and c3p if internal dc/dc converter is enabled, a 0.1 m f capacitor is required to connect these three pair of pins. v r and v f this is a feedback path for the gain control (external contrast con- trol) of vll1 to vll6. for adjusting the lcd driving voltage, it requires a feedback resistor placed between v r and v f , a gain con- trol resistor placed between v f and avss, a 10 m f capacitor placed between v r and avss. (refer to the application circuit) com0-com63, com64a and com64b (row drivers) these pins provide the row driving signal to lcd panel. output is 0v during display off. com64a and com64b are icon lines with same signal output so as to provide the ?exibility to have the icon line on top or bottom of panel, or both top and bottom of the panel. com64a/b also serves as the common driving signal in the icon mode. com64a/b is special design icon line (128 icons). there are some special commands to program it separately (e.g. set icon mask, smart icon mode, low power icon mode) seg0-seg127 (column drivers) these 128 pins provide lcd column driving signal to lcd panel. they output 0v during display off. avdd and avss avdd is the positive supply to the lcd bias internal dc/dc con- verter. avss is ground. vcc for using the internal dc/dc converter, a 0.1 m f capacitor from this pin to avss is required. it can also be an external bias input pin if internal dc/dc converter is not used. power is supplied to the lcd driving level selector and hv buffer cell with this pin. nor- mally, this pin is not intended to be a power supply to other compo- nent. dvdd and dvss power is supplied to the digital control circuit of the driver using these two pins. dvdd is power and dvss is ground. pin descriptions
3C289 mc141800a motorola operation of liquid crystal display driver description of block diagram module command decoder and command interface this module determines whether the input data is interpreted as data or command. data is directed to this module based upon the input of the d/ c pin. if d/ c high, data is written to graphic display data ram (gddram). d/ c low indicates that the input at d0-d7 is interpreted as a command. reset is of same function as power on reset (por). once res received the reset pulse, all internal circuitry will back to its initial sta- tus. refer to command description section for more information. mpu parallel 6800-series interface the parallel interface consists of 8 bi-directional data pins (d0- d7), r/ w, d/ c, ce and the clk. the r/ w input high indicates a read operation from the graphic display data ram (gddram). r/ w input low indicates a write operation to display data ram or internal command registers depending on the status of d/ c input. the clk input serves as data latch signal (clock). refer to ac operation con- ditions and characteristics section for parallel interface timing description. mpu serial iic interface the iic interface consists of two communication bus: data pin sda and clock pin clk. the clk input serves as data latch signal (clock). before communication begins, a start condition must be setup on the bus by the controller. to establish a start condition, the controller must pull the data pin low while the clock pin is high. after the start condition has been established for t hstart , an eight-bit address should be sent. the six most significant bits of the address (0111xy) are used to uniquely define devices on the bus, the 7th bit is used as a data / command control: if it is 0, then the signal on sda is interpreted as a command; if it is 1, then data sda is writ- ten to gddram. the least significant bit is a data direction read / write control; if it is 0, then the controller writes data / command to the driver; if it is 1, then the controller reads data / command from lcd driver. data is transferred with the most significant bit first. each byte has to be followed by an acknowledge bit. the transmitter releases the sda high during the acknowledge clock pulse. the receiver has to pull down the sda during the acknowledge clock pulse. to end communication, a stop condition should be set up on the bus. a low to high transition of data pin while the clock pin is high defines a stop condition. however, if a master still wishes to commu- nicate on the bus, another start condition and address can be gener- ated without a stop condition. refer to ac operation conditions and characteristics section for iic serial interface timing description. mpu serial peripheral interface the spi consists of 4 communication bus: data input pin din, data output pin dout, clock pin clk and chip enable pin ce. the clk input serves as data latch signal (clock). data is transferred serially with most significant bit first, least sig- nificant bit last. during the communication, the controller must input low ce before data transactions and must stay low for the rest of the transaction. by default, the lcd driver will receive command from mcu. if messages on the data pin are data rather than command, mcu should send data direction command (0100100x 0 ) to control the data direction and then one more command to define the number of data bytes will be read / write. after these two continuous com- mands are send, the following messages will be data rather than command. for read operation (x 0 = 1), mcu reads a group of data from lcd driver through dout pin. for write operation (x 0 = 0), mcu writes a group of data to the lcd driver through din pin. refer to ac operation conditions and characteristics section for serial peripheral interface timing description.
motorola 3C290 mc141800a figure 7. graphic display data ram (gddram) address map column address 00h column address 7fh page 1 page 2 lsb msb lsb msb com0 (com63) com63 (com0) seg0 seg127 row 0 note: the configuration in parentheses represent the remapping of rows and columns in 65 mux mode lsb row 64 page 9 com64 (icon) page 8 lsb msb row 63
3C291 mc141800a motorola display timing generator this module is an on chip low power rc oscillator circuitry (fig- ure 8). the oscillator frequency can be selected in the range of 15khz to 250khz by external resistor. one can enable the circuitry by software command. for external clock provided, feed the clock to osc2 and leave osc1 open. figure 8. oscillator circuitry lcd driving voltage generator and internal regulator this module generates the lcd voltage needed for display output. it takes a single supply input and generate necessary bias voltages. it consists of: 1. 4x and 5x dc-dc converter to generate the vcc voltage. 4x dc-dc converter is used for lcd panel which needs lower driving voltage for less power consump- tion. 5x dc-dc converter is used for lcd panel which needs higher driving voltage. 2. internal regulator feedback gain control for initial lcd voltage. it can also be used with external contrast control. 3. smart bias divider divide the lcd display voltage (v ll2 -v ll6 ) from the internal regu- lator output. this is a low power consumption circuit which can save the most display current compare with traditional resistor lad- der method. 4. contrast control block software control of 16 voltage levels of lcd voltage. all blocks can be individually turned off if external voltage genera- tor is employed 5. bias ratio selection circuitry software control of 1/7 and 1/9 bias ratio to match the characteris- tic of lcd panel. 6. self adjust temperature compensation circuitry provide 4 different compensation grade selections to satisfy the various liquid crystal temperature grades. the grading can be selected by software control. 65 bit latch / 128 bit latch a register carries the display signal information. first 65 bits are common driving signals and other 128 bits are segment driving sig- nals. data will be input to the hv-buffer cell for bumping up to the required level. level selector level selector is a control of the display synchronization. display voltage can be separated into two sets and used with different cycles. synchronization is important since it selects the required lcd voltage level to the hv buffer cell for output signal voltage pump. hv buffer cell (level shifter) hv buffer cell works as a level shifter which translates the low voltage output signal to the required driving voltage. the output is shifted out with an internal frm clock which comes from the display timing generator. the voltage levels are given by the level selector which is synchronized with the internal m signal. lcd panel driving waveform the following is an example of how the common and segment drivers may be connected to a lcd panel. the waveforms shown in figure 9a, 9b and 9c illustrate the desired multiplex scheme. in order to reduce the crosstalk effect, invert the polarities of the pixel-driving waveforms every 2 or 4 or 8 or 65 lines according to the selected waveforms. in the power-up state, the default waveform will be type b. figure 9a. lcd display example 0 graphic display data ram (gddram) the gddram is a bit mapped static ram holding the bit pattern to be displayed. the size of the ram is determined by number of row times the number of column (128x65 = 8320 bits). figure 7 is a description of the gddram address map. for mechanical flexibility, re-mapping on both segment and common outputs are provided. oscillation circuit enable2 osc1 osc2 feedback for internal oscillator for external clk input oscillator enable mc141800a external component buffer enable1 enable internal oscillator selected com1 com2 com3 com4 com5 com6 com7 seg1 seg2 seg3 seg4 com0 seg0
motorola 3C292 mc141800a figure 9b. lcd driving signal from mc141800a (waveform b) 123456 789 . . . time slot 65 vll6 vll5 vll4 vll3 vll2 vll1 com0 123456 789 . . . 65 123456 789 . . . 65 123456 789 . . . 65 vll6 vll5 vll4 vll3 vll2 vll1 com1 vll6 vll5 vll4 vll3 vll2 vll1 seg0 vll6 vll5 vll4 vll3 vll2 vll1 seg1 m
3C293 mc141800a motorola 123456 789 . . . 65 vll6 vll5 vll4 vll3 vll2 vll1 com0 123456 789 . . . 65 123456 789 . . . 65 123456 789 . . . 65 vll6 vll5 vll4 vll3 vll2 vll1 com1 vll6 vll5 vll4 vll3 vll2 vll1 seg0 vll6 vll5 vll4 vll3 vll2 vll1 seg1 . . . . . . . . . . . . m polarities inverted every 2 lines polarities inverted every 2 lines time slot figure 9c. lcd driving signal from mc141800a (waveform c with polarity inversion every 2 lines)
motorola 3C294 mc141800a command description set display on / off (display mode / stand-by mode) the display on command turns the lcd common and segment out- puts on. this command starts the conversion of data in gddram to necessary waveforms on the common and segment driving outputs. the on-chip bias generator is also turned on by this command. (note: oscillator on command should be sent before display on is selected) the display off command turn the display off and the states of the lcd driver are as follow during display off: 1. all the common and segment outputs are fixed at v ll1 (v ss ). 2. the bias internal dc/dc converter is turned off. 3. the ram and content of all registers are retained. 4. ic will accept new commands and data. the oscillator is not affected by this command. set gddram column address this command positions the address pointer on a column location. the address can be set to location 00h-7fh (128 columns). the col- umn address will be increased automatically after a read or write opera- tion. refer to address increment table and command set gddram page address for further information. set gddram page address this command positions the row address to 1 of 9 possible positions in gddram. refer to figure 7. master clear gddram this command is to clear the content of the display data ram to zero. issue this command followed by a dummy write command. the ram for icon line will not be affected by this command. master clear icon this command is a master clear of the icon data ram. after set- ting the page pointer to icon page (page 9), the internal icon ram data will be set to zero after the command is issued. before using this com- mand, set the page address to page 9 by the command set gddram page address. a dummy write data is also needed after the master clear icon command to make the clear icon action effective. set page mask (display mask) the following command will be written to the page mask register. page mask is an 8-bit register. each bit represents one of the 8 pages: page mask bit 0 represents page 1, page mask bit 1 represents page 2,...etc. page mask when the page mask is enabled, the display of those pages, with page mask bit set, will be cleared. meanwhile, the data in the display ram is retained. icon mask when the icon mask is enabled, the display of the icons will be cleared. meanwhile, the data in the icon display ram is retained. set display mode this command switch the driver to full display mode or icon display mode. in low power icon mode, only icons (driven by com64) are dis- played. display on row 0 to row 63 will be disabled. the dc-dc con- verter and the internal regulator are off. all vcc, vlls pins do not have external bias voltage supply in the low power icon mode. in normal display mode, com0 to com64 will be turned on. set display frequency in half display frequency mode, the display frame frequency will be halved. also, the operation frequency of analog circuitries will be halved for power saving purpose. save / restore column address save column address command saves a copy of the column address of gddram. restore column address command restores the copy obtained from the previous execution of saving column address. this instruction is very useful for writing full graphics characters that are larger than 8 pixels vertically. set column mapping this instruction selects the mapping of display data ram to seg- ment drivers for mechanical flexibility. there are 2 mappings to select: 1. column 0 - column 127 of gddram mapped to seg0-seg127 respectively; 2. column 0 - column 127 of gddram mapped to seg127-seg0 respectively. com64 will not be affected by this command. detail information please refer to section display output description. set row mapping this instruction selects the mapping of display data ram to com- mon drivers for mechanical flexibility. there are 2 selected mappings: 1. row 0 - row x of gddram to common 0 - common x respec- tively; 2. row 0 - row x of gddram to common x - common 0 respec- tively. (x+2 is the multiplex ratio) com64 will not be affected by this command. see section display output description for related information. set mux ratio this command is to select any a ratio from 2 to 65. row 64 (icon line) is not affected by this command and it would be turned on for normal display. this command contain two commands bytes, the first byte inform the driver that the second byte will be the no. of mux ratio. e.g. second byte = 0h to turn on row 0 and 64 (2 mux) second byte = 63h to turn on row 0 to 64 (65 mux) the unused common pins output non-scanning signals. set bias ratio this command sets the 1/7 bias or 1/9 bias for the divider output. the selection should match the characteristic of lcd panel. set oscillator disable / enable this command is used to either turn on / off oscillator. for using internal or external oscillator, this command should be executed. the setting for this command is not affected by command set display on/ off. see command ext/int oscillator for more information. set internal / external oscillator this command is used to select either internal or external oscillator. when internal oscillator is selected, feedback resistor between osc1 and osc2 is needed. for external oscillation circuit, feed clock input signal to osc2 and leave osc1 open. set internal dc/dc converter enable use this command to select the internal dc/dc converter to gener- ate the v cc from av dd . disable the internal dc/dc converter if exter- nal vcc is provided.
3C295 mc141800a motorola set 4x / 5x dc/dc converter this command selects the usage of 4x or 5x converter when the internal dc/dc converter is enabled. set temperature coefficient a temperature gradient selector circuit controlled by two control bits tc1 and tc2. this command can select 4 different lcd driving voltage temperature coefficients to match various liquid crystal temperature grades. set internal regulator on/off choose bit option 0 to disable the on chip internal regulator. choose bit option 1 to enables internal regulator which consists of the internal contrast control circuits. set smart bias divider on/off if the smart bias divider is disabled, external bias can be used for v ll6 to v ll2. if the smart bias divider is enabled, the internal circuit will generated the 1:7 or 1:9 bias driving voltage. end of command this command is used as extra write end command follows the last byte of data / command written. this command is not available if serial mode is selected. set internal contrast control enable this command is used to adjust the delta voltage of the bias volt- ages. with bit option = 1, the software selection for delta bias voltage control is enabled. with bit option = 0, internal contrast control is dis- abled. increase / decrease contrast level if the internal contrast control is enabled, this command is used to increase or decrease the contrast level within the 16 contrast levels. the contrast level starts from lowest value after por. set contrast level this command is to select one of the 16 contrast levels when internal contrast control circuitry is in use. after power-on reset, the contrast level is lowest. set smart icon mode this command is to set 4-phase or 6-phase smart icon modes which for lower vdd or higher von of panel. refer to smart icon mode output description for detail. set display waveform type this command will select the number of lines for the polarity inver- sion of the driving waveform. four types of waveform types are avail- able. refer to figure 9. set data direction this command is used in spi mode only. it will be two continuous commands, the first byte control the data direction and inform the lcd driver the second byte will be number of data bytes will be read / write. after these two commands sending out, the following messages will be data. command table bit pattern command comment 0000x 3 x 2 x 1 x 0 set gddram page address set gddram page address using x 3 x 2 x 1 x 0 as address bits. x 3 x 2 x 1 x 0 =0000 : page 1 (por) x 3 x 2 x 1 x 0 =0001 : page 2 x 3 x 2 x 1 x 0 =0010 : page 3 x 3 x 2 x 1 x 0 =0011 : page 4 x 3 x 2 x 1 x 0 =0100 : page 5 x 3 x 2 x 1 x 0 =0101 : page 6 x 3 x 2 x 1 x 0 =0110 : page 7 x 3 x 2 x 1 x 0 =0111 : page 8 x 3 x 2 x 1 x 0 =1000 : page 9 0001x 3 x 2 x 1 x 0 set contrast level with r/ w pin input low, set one of the 16 available values to the internal contrast register, using x 3 x 2 x 1 x 0 as data bits. the contrast register is reset to 0000 during por. 0010000x 0 set 4x / 5x dc-dc converter x 0 =0: enable 4x converter (por) x 0 =1: enable 5x converter 0010001x 0 set segment mapping x 0 =0: col0 to seg0 (por) x 0 =1: col0 to seg127 0010010x 0 set common mapping x 0 =0: row0 to com0 (por) x 0 =1: row0 to com63 0010100x 0 set display on/off x 0 =0: display off (por) x 0 =1: display on 0010101x 0 set internal dc/dc converter on/off x 0 =0: internal dc/dc converter off (por) x 0 =1: internal dc/dc converter on 0010110x 0 set internal regulator on/off x 0 =0: internal regulator off(por) x 0 =1: internal regulator on 0010111x 0 set smart bias divider on/off x 0 =0: smart bias divider off (por) x 0 =1: smart bias divider on when an external bias network is preferred, the smart bias divider should be disabled.
motorola 3C296 mc141800a command table bit pattern command comment 0011000x 0 set internal contrast control on/off x 0 =0: internal contrast control off(por) x 0 =1: internal contrast control on internal contrast circuits can be disabled if external contrast cir- cuits is preferred. 0011001x 0 set display frequency x 0 =0 : normal display frequency (por) x 0 =1 : half display frequency 0011010x 0 save/restore gddram column address x 0 =0 : restore address x 0 =1 : save address 00110110 master clear gddram master clear gddram (64 x 128 bits), row 64 (icon line) will not be cleared 00110111 master clear icons master clear of icons 0011100x 0 set bias ratio x 0 =0 : bias = 1 : 9 (por) x 0 =1 : bias = 1 : 7 0011101x 0 reserved x 0 =0 : normal operation (por) x 0 =1 : test mode 1 select (note : make sure to set x 0 =0 during application) 00111100 end of command write command to identify end of data frame 0011111x 0 set display mode x 0 =0 : low power icon display mode x 0 =1 : normal display mode (por) 01000000 set multiplex ratio next command will de?ne no. of mux, 00x 5 x 4 x 3 x 2 x 1 x 0 no. of mux=00111111 upon por (65 mux) 01000001 set page mask next command will be written to page mask register page mask register=0 upon por 0100010x 0 page mask x 0 =0 : disable page mask (por) x 0 =1 : enable page mask 0100011x 0 icon mask x 0 =0 : disable icon mask (por) x 0 =1 : enable icon mask 0100100x 0 set data direction (for spi mode only) x 0 =0 : write data (por) x 0 =1 : read data next command will de?ne the total number of data bytes will be read / write e.g. no. of data bytes = 01111111 for 128 bytes 0100101x 0 reserved x 0 =0 : select switch resistor as hv divider (por) x 0 =1 : select buffer as hv dividier 0100110x 0 reserved x 0 =0 : select 500ohm in switch resistor divider (por) x 0 =1 : select 1kohm in switch resistor divider 01010100 reserved next command will de?ne smart divider value, 000x 4 x 3 x 2 x 1 x 0 0101001x 0 reserved x 0 =0 : use diode approach for temperature compensation (por) x 0 =1 : use band gap technique for temperature compensation 011001x 1 x 0 set display waveform type x 1 x 0 =00 : waveform type b (por) x 1 x 0 =01 : waveform type c with polarity inversion every 8 lines x 1 x 0 =10 : waveform type c with polarity inversion every 4 lines x 1 x 0 =11 : waveform type c with polarity inversion every 2 lines 0110100x 0 set smart icon mode x 0 =1 : 4-phase smart icon x 0 =0 : 6-phase smart icon (por) 011011x 1 x 0 set temperature coef?cient x 1 x 0 =: 0.00% (por) x 1 x 0 =: -0.18% x 1 x 0 =: -0.22% x 1 x 0 =: -0.35% 0111000x 0 increase / decrease contrast level x 0 =0: decrease by one level x 0 =1: increase by one level (note: increment/decrement wraps round among the 16 contrast levels. start at the lowest level when por.
3C297 mc141800a motorola data read / write to read data from the gddram, input high to r/ w pin and d/ c pin in parallel mode or pull high at the 7th and 8th bit of the address in iic serial mode or send data direction command 01001001 in spi mode. data is valid at the falling edge of clk. and the gddram column address pointer will be increased by one automatically. to write data to the gddram, input low to r/ w pin and high to d/ c pin in parallel mode or pull low 7th bit and high 8th bit of the address in iic serial mode or send data direction command 01001000 in spi mode. data is latched at the falling edge of clk. and the gddram column address pointer will be increased by one automatically. if parallel interface is selected, end of command should be followed after all data are send out. no auto address pointer increment will be performed for the dummy write data after master clear gddram. (refer to the commands required for r/ w actions on ram table) address increment table (automatic) address increment is done automatically data read write. the column address pointer of gddram *3 is affected. remarks: *1. only data is read from ram. *2. if write data is issued after command clear ram, address increase is not applied. *3. column address will wrap round when overflow. d/ cr/ w comment address increment remarks 0 0 write command no 0 1 read command no (invalid mode) *1 1 0 write data yes *2 1 1 read data yes commands required for r/w actions on ram * no need to resend the command again if it is set previously. the read / write action to the display data ram does not depend on the display mode. this means the user can change the ram content whether the target ram content is being displayed. r/w actions on rams commands required read/write data from/to gddram. set gddram page address set gddram column address read/write data end of command (0000x 3 x 2 x 1 x 0 )* (1x 6 x 5 x 4 x 3 x 2 x 1 x 0 )* (x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 ) (00111100) save/restore gddram column address. save/restore gddram column address end of command (0011010x 0 ) (00111100) master clear gddram set clear page gddram (64 x 128 bits) dummy write data (00110110) (x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 ) master clear icon ram set gddram page address to page 9 master clear icon ram (128 bits, row 64) dummy write data (00001000) (00110111) (x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 ) command table bit pattern command comment 0111011x 0 reserved x 0 =0: normal operation (por) x 0 =1: test mode 2 select (note: make sure to set x 0 =0 during application) 0111101x 0 set internal / external oscillator x 0 =0: internal oscillator (por) x 0 =1: external oscillator. for internal oscillator place a resistor between osc1 and osc2. for external oscillator mode, feed clock input to osc2. 0111111x 0 set oscillator on/off x 0 =0: oscillator off (por) x 0 =1: oscillator on. this is the master control for oscillator circuitry. this command should be issued after the set internal / external oscillator com- mand. 1x 6 x 5 x 4 x 3 x 2 x 1 x 0 set gddram column address set gddram column address. use x 6 x 5 x 4 x 3 x 2 x 1 x 0 as address bits.
motorola 3C298 mc141800a display output description this is an example of output pattern on the lcd panel. figure 10b and 10c are data map of gddram and the output pattern on the lcd display with different command enabled. content of gddram page 1 upper nibble lower nibble 5a5a5a5a5a---------5a5a5a5a5a 5a5a5a5a5a---------5a5a5a5a5a page 2 upper nibble lower nibble 33cc33cc33---------cc33cc33cc 33cc33cc33---------cc33cc33cc page 3 upper nibble lower nibble 0000ffff00---------ff0000ffff ffff0000ff---------00ffff0000 page 4 upper nibble lower nibble ffffffff00---------ff00000000 ffffffff00---------ff00000000 . . . . . . . . . page 9 upper nibble lower nibble 0000000000---------0000000000 0001110000---------0000111000 figure 10c. examples of lcd display with different command enabled figure 10b figure 10a com0 com63 seg0 seg127 com64 column remap enable row re-map disable column remap disable row re-map disable column remap disable row re-map enable icon line
3C299 mc141800a motorola power up sequence (commands required) command required por status remarks set display frequency set oscillator enable set mux ratio set bias ratio set internal dc/dc converter set internal regulator on set temperature coef?cient set internal contrast control on set contrast level set smart bias divider on set segment mapping set common mapping set display on normal disable 65 mux 1/9 bias 4x converter off tc=0% off contrast level = 0 off seg. 0 = col. 0 com. 0 = row 0 off *1 *1 *1 *1 *1 *1 *1, *3 *1, *3 *1, *2, *3 *1 remarks: *1 -- required only if desired status differ from por. *2 -- effective only if internal contrast control is enabled. *3 -- effective only if internal regulator is enabled. figure 11b. lcd driving signal for 6 - phase smart icon mode figure 11a. lcd driving signal for 4 - phase smart icon mode smart icon mode output description there are two driving schemes of smart icon mode for panel with different v on /v off or v dd : 1) 4 - phase smart icon: 1/4 ~ 3/4 v off > v dd * sqrt (1/4) v on < v dd * sqrt (3/4) 2) 6 - phase smart icon: 1/6 ~ 3/6 v off > v dd * sqrt (1/6) v on < v dd * sqrt (3/6) com (non icon) com64(icon) seg(on) seg(off) dvdd dvss dvdd dvss dvdd dvss dvdd dvss com (non icon) com64(icon) seg(on) seg(off) dvdd dvss dvdd dvss dvdd dvss dvdd dvss
motorola 3C300 mc141800a vr vf c3p c3n osc1 osc2 to lcd panel com0 to com64 seg0 to seg127 cmos mpu/mcu ram eprom res clk mc141800a c2p c2n c1p c1n application circuit: remark: 1. r3 can be omitted for external oscillator. 2 . res should be at a known state. 3. vll2 - vll6 can be left open for internal divider is enable. 4. r/ w, ce, d/ c and d3-d6 can be open for iic serial mode. 5. d1/a1 and d2/a2 should be at predefined state for device identification. all internal analog circuitry disabled at iic serial mode operation s/ p scl sda d0/sda v dd d1/a1 d2/a2 iic address r3 vll2 vll3 vll4 vll5 vll6 vcc dvss dvdd avdd avss 0.1 m f 0.1 m f dv dd av dd v cc d7/iic/ spi v dd r r 6. r is pull up resistance, r < t r 2 * c bus (r = 300 ohm for 1mhz, assume c bus = 200pf)
3C301 mc141800a motorola vr vf c3p c3n osc1 osc2 0.1 m f to lcd panel com0 to com64 seg0 to seg127 cmos mpu/mcu ram eprom res scl sda mc141800a c2p c2n c1p c1n 0.1 m f 0.1 m f remark: 1. r3 can be omitted for external oscillator. 2. vr and vf can be left open for internal regulator disable and contrast disable. 3. res should be at a known state. 4. r/ w, ce, d/ c and d3-d6 can be open for iic serial mode. 5. d1/a1 and d2/a2 should be at predefined state for device identification. vll2 vll4 vll3 vll6 vll5 all internal analog circuitry enabled at iic serial mode operation clk d0/sda d1/a1 d2/a2 s/ p v dd iic address r3 vcc 0.1 m f dvss dvdd avdd avss 0.1 m f 0.1 m f dv dd av dd d7/iic/ spi v dd r r 6. r is pull up resistance, r < t r 2 * c bus (r = 300 ohm for 1mhz, assume c bus = 200pf)
motorola 3C302 mc141800a vr vf c3p c3n osc1 osc2 to lcd panel com0 to com64 seg0 to seg127 cmos mpu/mcu ram eprom res clk mc141800a c2p c2n c1p c1n s/ p sck miso d4/dout v dd r3 vll2 vll3 vll4 vll5 vll6 vcc dvss dvdd avdd avss 0.1 m f 0.1 m f dv dd av dd v cc remark: 1. r3 can be omitted for external oscillator. 2 . res should be at a known state. 3. vll2 - vll6 can be left open for internal divider is enable. 4. r/ w, d/ c, d0-2 and d5-6 can be open for spi serial mode. all internal analog circuitry disabled at spi serial mode operation ce mosi d3/din d7/iic/ spi
3C303 mc141800a motorola vr vf c3p c3n osc1 osc2 to lcd panel com0 to com64 seg0 to seg127 cmos mpu/mcu ram eprom res clk mc141800a c2p c2n c1p c1n s/ p sck miso d4/dout v dd r3 dvss dvdd 0.1 m f dv dd remark: 1. r3 can be omitted for external oscillator. 2. vr and vf can be left open for internal regulator disable and contrast disable. 3 . res should be at a known state. 4. r/ w, d/ c, d0-2 and d5-6 can be open for spi serial mode. all internal analog circuitry enabled at spi serial mode operation ce mosi d3/din d7/iic/ spi 0.1 m f 0.1 m f 0.1 m f vll2 vll4 vll3 vll6 vll5 vcc 0.1 m f avdd avss 0.1 m f av dd
motorola 3C304 mc141800a vr vf c3p c3n osc1 osc2 to lcd panel com0 to com64 seg0 to seg127 cmos mpu/mcu with parallel interface ram eprom res clk mc141800a c2p c2n c1p c1n s/ p r3 vll2 vll3 vll4 vll5 vll6 vcc dvss dvdd avdd avss 0.1 m f 0.1 m f dv dd av dd v cc remark: 1. r3 can be omitted for external oscillator. 2 . res should be at a known state. 3. vll2 - vll6 can be left open for internal divider is enable. all internal analog circuitry disabled at parallel mode operation ce d0 .. d7 r/ w d/ c
3C305 mc141800a motorola vr vf c3p c3n osc1 osc2 to lcd panel com0 to com64 seg0 to seg127 cmos mpu/mcu with parallel interface ram eprom res clk mc141800a c2p c2n c1p c1n s/ p r3 dvss dvdd 0.1 m f dv dd remark: 1. r3 can be omitted for external oscillator. 2. vr and vf can be left open for internal regulator disable and contrast disable. 3 . res should be at a known state. all internal analog circuitry enabled at parallel mode operation ce d0 .. d7 r/ w d/ c 0.1 m f 0.1 m f 0.1 m f vll2 vll4 vll3 vll6 vll5 vcc 0.1 m f avdd avss 0.1 m f av dd
motorola 3C306 mc141800a package dimensions mc141800at tab package dimension - 1 (do not scale this drawing) reference: 98asl00269a issue 0 released on 11 feb 97
3C307 mc141800a motorola package dimensions mc141800at tab package dimension - 2 (do not scale this drawing) reference: 98asl00269a issue 0 released on 11 feb 97
motorola 3C308 mc141800a die pad coordinate of mc141800a pad name x(um) y(um) pad name x(um) y(um) pad name x(um) y(um) pad name x(um) y(um) pad name x(um) y(um) 1 com(22) -4826.0 -807.6 61 c3p 1198.4 -857.8 121 seg(0) 4826.0 807.6 181 seg(60) 266.0 807.6 241 seg(120) -4294.0 807.6 2 com(23) -4750.0 -807.6 62 c3n 1304.4 -857.8 122 seg(1) 4750.0 807.6 182 seg(61) 190.0 807.6 242 seg(121) -4370.0 807.6 3 com(24) -4674.4 -811.8 63 vll2: 1410.4 -857.8 123 seg(2) 4674.0 807.6 183 seg(62) 114.0 807.6 243 seg(122) -4446.0 807.6 4 com(25) -4598.0 -807.6 64 vll2: 1516.4 -857.8 124 seg(3) 4598.0 807.6 184 seg(63) 38.0 807.6 244 seg(123) -4522.0 807.6 5 com(26) -4522.0 -807.6 65 vll3: 1622.4 -857.8 125 seg(4) 4522.0 807.6 185 seg(64) -38.0 807.6 245 seg(124) -4598.0 807.6 6 com(27) -4446.0 -807.6 66 vll3: 1728.4 -857.8 126 seg(5) 4446.0 807.6 186 seg(65) -114.0 807.6 246 seg(125) -4674.0 807.6 7 com(28) -4370.0 -807.6 67 vll4: 1834.4 -857.8 127 seg(6) 4370.0 807.6 187 seg(66) -190.0 807.6 247 seg(126) -4750.0 807.6 8 com(29) -4294.0 -807.6 68 vll4: 1940.4 -857.8 128 seg(7) 4294.0 807.6 188 seg(67) -266.0 807.6 248 seg(127) -4826.0 807.6 9 com(30) -4218.0 -807.6 69 vll5: 2046.4 -857.8 129 seg(8) 4218.0 807.6 189 seg(68) -342.0 807.6 249 com64b -5328.4 835.4 10 com(31) -4142.0 -807.6 70 vll5: 2152.4 -857.8 130 seg(9) 4142.0 807.6 190 seg(69) -418.0 807.6 250 com(0) -5328.4 759.4 11 dvdd: -4042.2 -857.8 71 vll6: 2258.4 -857.8 131 seg(10) 4066.0 807.6 191 seg(70) -494.0 807.6 251 com(1) -5328.4 683.4 12 s/p -3940.6 -857.8 72 vll6: 2364.4 -857.8 132 seg(11) 3990.0 807.6 192 seg(71) -570.0 807.6 252 com(2) -5328.4 607.4 13 res -3839.0 -857.8 73 dvss: 2470.4 -857.8 133 seg(12) 3914.0 807.6 193 seg(72) -646.0 807.6 253 com(3) -5328.4 531.4 14 d/c -3737.4 -857.8 74 osc1 2576.4 -857.8 134 seg(13) 3838.0 807.6 194 seg(73) -722.0 807.6 254 com(4) -5328.4 455.4 15 dvss: -3569.0 -857.8 75 dvss: 2682.4 -857.8 135 seg(14) 3762.0 807.6 195 seg(74) -798.0 807.6 255 com(5) -5328.4 379.4 16 dvss: -3467.4 -857.8 76 dvss: 2788.4 -857.8 136 seg(15) 3686.0 807.6 196 seg(75) -874.0 807.6 256 com(6) -5328.4 303.4 17 dvss: -3365.8 -857.8 77 vcc: 2894.4 -857.8 137 seg(16) 3610.0 807.6 197 seg(76) -950.0 807.6 257 com(7) -5328.4 227.4 18 dvss: -3264.2 -857.8 78 vcc: 3000.4 -857.8 138 seg(17) 3534.0 807.6 198 seg(77) -1026.0 807.6 258 com(8) -5328.4 151.4 19 dvss: -3162.6 -857.8 79 avss: 3106.4 -857.8 139 seg(18) 3458.0 807.6 199 seg(78) -1102.0 807.6 259 com(9) -5328.4 75.4 20 dvss: -3061.0 -857.8 80 osc2 3212.4 -857.8 140 seg(19) 3382.0 807.6 200 seg(79) -1178.0 807.6 260 com(10) -5328.4 -0.6 21 dvss: -2959.4 -857.8 81 avdd: 3318.4 -857.8 141 seg(20) 3306.0 807.6 201 seg(80) -1254.0 807.6 261 com(11) -5328.4 -76.6 22 dvss: -2857.8 -857.8 82 dvss: 3493.0 -857.8 142 seg(21) 3230.0 807.6 202 seg(81) -1330.0 807.6 262 com(12) -5328.4 -152.6 23 dvss: -2756.2 -857.8 83 dvss: 3594.6 -857.8 143 seg(22) 3154.0 807.6 203 seg(82) -1406.0 807.6 263 com(13) -5328.4 -228.6 24 dvss: -2654.6 -857.8 84 dvss: 3696.2 -857.8 144 seg(23) 3078.0 807.6 204 seg(83) -1482.0 807.6 264 com(14) -5328.4 -304.6 25 dvss: -2553.0 -857.8 85 dvss: 3797.8 -857.8 145 seg(24) 3002.0 807.6 205 seg(84) -1558.0 807.6 265 com(15) -5328.4 -380.6 26 dvss: -2451.4 -857.8 86 dvss: 3899.4 -857.8 146 seg(25) 2926.0 807.6 206 seg(85) -1634.0 807.6 266 com(16) -5328.4 -456.6 27 dvss: -2349.8 -857.8 87 dvss: 4001.0 -857.8 147 seg(26) 2850.0 807.6 207 seg(86) -1710.0 807.6 267 com(17) -5328.4 -532.6 28 dvss: -2248.2 -857.8 88 com64a 4142.0 -807.6 148 seg(27) 2774.0 807.6 208 seg(87) -1786.0 807.6 268 com(18) -5328.4 -608.6 29 dvss: -2146.6 -857.8 89 com(63) 4217.0 -806.2 149 seg(28) 2698.0 807.6 209 seg(88) -1862.0 807.6 269 com(19) -5328.4 -684.6 30 dvss: -2045.0 -857.8 90 com(62) 4293.0 -806.2 150 seg(29) 2622.0 807.6 210 seg(89) -1938.0 807.6 270 com(20) -5328.4 -760.6 31 dvss: -1943.4 -857.8 91 com(61) 4369.0 -806.2 151 seg(30) 2546.0 807.6 211 seg(90) -2014.0 807.6 271 com(21) -5328.4 -836.6 32 dvss: -1841.8 -857.8 92 com(60) 4445.0 -806.2 152 seg(31) 2470.0 807.6 212 seg(91) -2090.0 807.6 33 dvss: -1740.2 -857.8 93 com(59) 4521.0 -806.2 153 seg(32) 2394.0 807.6 213 seg(92) -2166.0 807.6 34 r/w -1638.6 -857.8 94 com(58) 4597.0 -806.2 154 seg(33) 2318.0 807.6 214 seg(93) -2242.0 807.6 35 d7 -1537.0 -857.8 95 com(57) 4673.0 -806.2 155 seg(34) 2242.0 807.6 215 seg(94) -2318.0 807.6 36 d6 -1435.4 -857.8 96 com(56) 4749.0 -806.2 156 seg(35) 2166.0 807.6 216 seg(95) -2394.0 807.6 37 d5 -1333.8 -857.8 97 com(55) 4826.0 -807.6 157 seg(36) 2090.0 807.6 217 seg(96) -2470.0 807.6 38 d4 -1232.2 -857.8 98 com(54) 5328.4 -836.6 158 seg(37) 2014.0 807.6 218 seg(97) -2546.0 807.6 39 d3 -1130.6 -857.8 99 com(53) 5328.4 -760.6 159 seg(38) 1938.0 807.6 219 seg(98) -2622.0 807.6 40 d2 -1029.0 -857.8 100 com(52) 5328.4 -684.6 160 seg(39) 1862.0 807.6 220 seg(99) -2698.0 807.6 41 d1 -927.4 -857.8 101 com(51) 5328.4 -608.6 161 seg(40) 1786.0 807.6 221 seg(100) -2774.0 807.6 42 d0 -825.8 -857.8 102 com(50) 5328.4 -532.6 162 seg(41) 1710.0 807.6 222 seg(101) -2850.0 807.6 43 d0 -724.2 -857.8 103 com(49) 5328.4 -456.6 163 seg(42) 1634.0 807.6 223 seg(102) -2926.0 807.6 44 clk -622.6 -857.8 104 com(48) 5328.4 -380.6 164 seg(43) 1558.0 807.6 224 seg(103) -3002.0 807.6 45 clk -521.0 -857.8 105 com(47) 5328.4 -304.6 165 seg(44) 1482.0 807.6 225 seg(104) -3078.0 807.6 46 ce -419.6 -857.8 106 com(46) 5328.4 -228.6 166 seg(45) 1406.0 807.6 226 seg(105) -3154.0 807.6 47 dvdd: -317.8 -857.8 107 com(45) 5328.4 -152.6 167 seg(46) 1330.0 807.6 227 seg(106) -3230.0 807.6 48 dvdd: -216.2 -857.8 108 com(44) 5328.4 -76.6 168 seg(47) 1254.0 807.6 228 seg(107) -3306.0 807.6 49 dvss: -114.6 -857.8 109 com(43) 5328.4 -0.6 169 seg(48) 1178.0 807.6 229 seg(108) -3382.0 807.6 50 dvss: -13.0 -857.8 110 com(42) 5328.4 75.4 170 seg(49) 1102.0 807.6 230 seg(109) -3458.0 807.6 51 avdd: 138.4 -857.8 111 com(41) 5328.4 151.4 171 seg(50) 1026.0 807.6 231 seg(110) -3534.0 807.6 52 avdd: 244.4 -857.8 112 com(40) 5328.4 227.4 172 seg(51) 950.0 807.6 232 seg(111) -3610.0 807.6 53 avss: 350.4 -857.8 113 com(39) 5328.4 303.4 173 seg(52) 874.0 807.6 233 seg(112) -3686.0 807.6 54 avss: 456.4 -857.8 114 com(38) 5328.4 379.4 174 seg(53) 798.0 807.6 234 seg(113) -3762.0 807.6 55 vf 562.4 -857.8 115 com(37) 5328.4 455.4 175 seg(54) 722.0 807.6 235 seg(114) -3838.0 807.6 56 vr 668.4 -857.8 116 com(36) 5328.4 531.4 176 seg(55) 646.0 807.6 236 seg(115) -3914.0 807.6 57 c1p 774.4 -857.8 117 com(35) 5328.4 607.4 177 seg(56) 570.0 807.6 237 seg(116) -3990.0 807.6 58 c1n 880.4 -857.8 118 com(34) 5328.4 683.4 178 seg(57) 494.0 807.6 238 seg(117) -4066.0 807.6 59 c2p 986.4 -857.8 119 com(33) 5328.4 759.4 179 seg(58) 418.0 807.6 239 seg(118) -4142.0 807.6 60 c2n 1092.4 -857.8 120 com(32) 5328.4 835.4 180 seg(59) 342.0 807.6 240 seg(119) -4218.0 807.6 note : *power and ground die pads should be bonded correspondingly in cog application die pad 15 - 33, 43, 45, 47 -54, 64, 66, 68, 70, 72 - 73, 76, 78 and 82 - 87 are multiple pads of critical signal (basically, these are d0, clk, dvdd, dvss, avdd, avss, vcc and vll2-vll6 which special design for cog) bump size : pad x(um) y(um) die size (including scribe) : 11226.8 x 2286 (um) 1-10 42 100 11-87 65 65 88-97 42 100 98-120 100 42 121-248 42 100 249-271 100 42

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